Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photoconversion device to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a block diagram of an exemplary CMOS imager device 308 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the timing and control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. The control circuit 250 also controls the row and column driver circuitry 210, 260 such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig), are read by a sample and hold circuit 261 associated with the column device 260. A differential signal (Vrst−Vsig) is produced by differential amplifier 262 for each pixel which is digitized by analog to digital converter 275 (ADC). The analog to digital converter 275 supplies the digitized pixel signals to an image processor 280 which forms a digital image.
In a digital CMOS imager, when incident light strikes the surface of a photodiode, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. The photo charge moves from the initial charge accumulation region to the floating diffusion region or it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by a source follower transistor (described above).
Conventional CMOS imagers typically have difficulty fully transferring the photogenerated charge from the photodiode to the floating diffusion region. One problem with transferring charge occurs if die n-type silicon layer of the photodiode is located close to the surface which causes a certain amount of electron/carrier recombination due to surface defects. Electron/carrier recombination needs to be reduced to achieve good charge transfer to the floating diffusion region. Another obstacle to complete charge transference arc potential barriers which exist at the gate of a transfer transistor.
Digital imagers may utilize a pixel containing a p-n-p photodiode 49, an example of which is shown in FIG. 2. The pixel sensor cell shown in FIG. 2 has a p-type substrate 60 with a p-well 61. In the illustrated example, a p-type layer 10 of photodiode 49 is located closest to the surface of substrate 60 and an n-type layer 12 is buried between the p-type layers 10, 60. The p-n-p photodiode 49 has some drawbacks. First, there can be a lag problem with pixels having transfer transistors 18 for transferring charge to the floating diffusion region 14 because during the integration time the electron carriers are collected in the sandwiched n-layer 12 and then transferred to the floating diffusion region 14 through a transfer gate 18. In order to fully utilize the generated electron carrier it is necessary to eliminate two energy barriers to reach the floating diffusion region, between the photodiode and the transfer gate and between the transfer gate and floating diffusion region. Charge leakage is another problem associated with the conventional p-n-p photodiode 49. That is, when the transfer transistor 18 gate length is too short, sub-threshold current becomes significantly high due to charge breakdown between n-type layers of both sides of the transfer gate channel.